Prescaler circuits generate an output signal that is a fractional scale factor related to the input signal. The output signal is synchronous and proportional in frequency to a clock signal. Some circuits provide an unbalanced duty cycle which is at a fixed rate. A clock signal output of a duty cycle unbalanced prescaler is fixed, for example, to:
(1). 1 cycles low and N/2 cycles high, when the prescaler value N is an even number and 1&lt;N&gt;15. PA1 (2). 1.5 cycle low and N/2-1.5 cycles high, when prescaler value N is an odd number and 2&lt;N&lt;16. PA1 (3). 4 cycle low and N/2-4 cycles high, when prescaler value N is an even number and 15&gt;N&gt;63. PA1 (4). 4.5 cycle low and N/2-4.5 cycles high, when prescaler value is an odd number and 16&lt;N&lt;64.
This scheme results in a duty cycle unbalanced clock. This causes problems in high frequency designs because of the narrow clock pulse. This design is technology dependent.
Alternate solutions have been used using digital phase lock loop (DPLL) which can yield a 50% duty cycle most of the time. The main draw-back is that this approach requires more silicon space on an integrated circuit chip, and thus more power.
A 50% duty cycle divide-by-N counter is described in U.S. Pat. No. 5,127,036. The described circuit generates a duty cycle output clock signal having a fifty percent duty cycle.
U.S. Pat. No. 5,491,440, describes a circuit for automatically adjusting the duty cycle of an output clock. The circuit utilizes a D-type flip-flop and requires an input of a referenced voltage, a reset signal, and input clock signal.